Electronics
Saleh Naghizade; Hamed Saghaei
Abstract
This paper reports a new optical half-adder design using linear defects in a photonic crystal (PhC) structure. The half adder's proper design obviates the need to increase the input signal's intensity for the nonlinear optical Kerr effect's appearance, which leads to the diversion of the incoming light ...
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This paper reports a new optical half-adder design using linear defects in a photonic crystal (PhC) structure. The half adder's proper design obviates the need to increase the input signal's intensity for the nonlinear optical Kerr effect's appearance, which leads to the diversion of the incoming light toward the desired output. The proposed device is composed of silicon rods consisting of four optical waveguides and a defect in a PhC. Two well-known plane wave expansion and finite difference time domain methods are used to study and analyze photonic band structure and light propagation inside the PhC, respectively. The numerical results demonstrate that the ON-OFF contrast ratios are 16 dB for “Sum” and about 14 dB for "Carry". They also reveal that the proposed half-adder has a maximum time delay of 0.8 ps with a total footprint of 158 µm2. Due to very low delay time, high contrast ratio, and small footprint, they are more crucial in modern optoelectronic technologies, so this structure can be used in the next generation of all-optical high-speed central processing units.
Electronics
Mahdi Taheri; Saeideh Sheikhpour; Mohammad Saeed Ansari; Ali Mahani
Abstract
This paper introduces a high-Speed fault-resistant hardware implementation for the S-box of AES cryptographic algorithm, called HFS-box. A deep pipelining for S-box at the gate level is proposed. In addition, in HFS-box a new Dual Modular Redundancy based (DMR-based) countermeasure is exploited for fault ...
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This paper introduces a high-Speed fault-resistant hardware implementation for the S-box of AES cryptographic algorithm, called HFS-box. A deep pipelining for S-box at the gate level is proposed. In addition, in HFS-box a new Dual Modular Redundancy based (DMR-based) countermeasure is exploited for fault correction purpose. The newly introduced countermeasure is a fault correction scheme based on DMR technique (FC-DMR) combined with a version of the time redundancy technique. In the proposed architecture, when a transient random or malicious fault(s) is detected in each pipeline stage, the error signal corresponding to that stage becomes high. The control unit holds the previous correct value in the output of our proposed DMR voter in the other pipeline stages as soon as it observes the value ‘1’ on the error signal. The previous correct outputs will be kept until the fault effect disappears. The presented low-cost HFS-box provide a high capability of fault resistance against transient faults with any duration by imposing low area overhead compared with similar fault correction strategies, i.e. 137%, and low throughput degradation, i.e. 11.3%, on the original S-box implementation.