Hardware Design and Implementation of a Low-Cost and Efficient FPGA-based MIMO-OFDM System for Wireless Video Transmission in Embedded Systems

Wijesekara, Patikiri Arachchige Don Shehan Nilmantha; Wickramasinghe, Athapattu Mudiyanselage Shavindya Deshani; Chinthaka, Pitiya Kankanamge Dulan; Weeraarachchi, Weebadu Arachchige Piyumi Malkisara

doi:10.22055/jaree.2026.48526.1145

Hardware Design and Implementation of a Low-Cost and Efficient FPGA-based MIMO-OFDM System for Wireless Video Transmission in Embedded Systems

Articles in Press

Document Type : Research article

Authors

Patikiri Arachchige Don Shehan Nilmantha Wijesekara ¹

Athapattu Mudiyanselage Shavindya Deshani Wickramasinghe ²

Pitiya Kankanamge Dulan Chinthaka ²

Weebadu Arachchige Piyumi Malkisara Weeraarachchi ²

¹ Department of Electrical and Information Engineering, Faculty of Engineering, University of Ruhuna

² Department of Electrical and Information Engineering, Faculty of Engineering, University of Ruhuna, Galle 80000, Sri Lanka

10.22055/jaree.2026.48526.1145

Abstract

We find that existing Multiple-Input-Multiple-Output (MIMO)-Orthogonal Frequency Division Multiplexing (OFDM) designs incur high implementation resource cost, latency, and power consumption and are thus less suitable to be deployed in resource-constrained embedded systems. Therefore, in this paper, we design a low-cost and efficient FPGA-based MIMO-OFDM system with reconfigurable modulation schemes and pilot symbols suitable for wireless video transmission. We utilize Karatsuba-like multiplications to implement complex multipliers and use efficient IP cores for fast Fourier transforms in OFDM by using clock gating. Further, we use shift register chains, magnitude approximation, and shift register-based correlators for efficient synchronization. Further, a hybrid 3-stage BCH code (22, 15) is used to combat pixel-wise errors using a hybrid approach of pre-computed lookup tables, a simplified third-degree generator polynomial, and parallel parity bit computation. Moreover, a two-level hierarchical 4x4 pixel hybrid inter- and intra-pixel interleaver is used to combat burst errors. We use the least squares method to approximate the 4x4 channel matrix using a pre-computed intermediate pilot matrix and then approximate a Moore-Penrose pseudo-matrix inverse by using an adaptive singular value decomposition considering the infinity-norm of differences and SNR regularization for channel equalization using a zero-forcing detector. Furthermore, we use fixed-point arithmetic, clock division inside modules, value truncation, resource sharing among 4 spatial streams using time division multiplexing, and pipelining within the OFDM stages to achieve the preceding objectives. Thereafter, the designed system is verified using extensive simulations, implemented in Xilinx FPGAs, and tested for error resilience, latency, throughput, and power consumption compared with existing studies.

Keywords

Field programmable gate array

Orthogonal frequency division multiplexing

Video communication

Subjects