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A Fourth-order MASH DDSM for Accurate Fractional Frequency Synthesizers

Document Type : Research article

Author

Department of Electrical Engineering, Shoushtar Branch, Islamic Azad University, Shoushtar 64517-41117, Iran

Abstract

The output of a Digital Delta-Sigma Modulator (DDSM) is always a periodic signal and the input is constant. A hybrid DDSM is a premiere to its conventional counterpart for having a potential speed, by the choice of its smaller bus. This paper offers an implementation for multi-stage noise shaping (MASH) DDSMs that includes four modulators named hybrid DDSM-1, DDSM-2, DDSM-3, and DDSM-4. Also, it introduces a new solution, where the desired ratio in fractional frequency synthesizers is formed by combining four different modulos. The first stage modulator is a programmable modulus EFM1 and has a modulus M1 that is not a power of 2. The second, third, and fourth stage modulators are modified MASH 1-1, multi-modulus MASH 1-1-1, and the efficiently dithered MASH 1-1-1-1 modulator that has conventional modulus  M2, M3, and M4, respectively. The M1 modulus is optimally selected to synthesize the new structure of the desired frequencies. Design results confirm the suppositional predictions. In addition, the results of the circuit implementation proposed method offer a 17% reduction in hardware complexity.

Highlights

  • Proposing a novel design method for digital delta-sigma modulators (DDSMs) that can be used for precision frequency synthesizers.
  • Proposing a 4th order modulator with a multi-stage structure in which each stage is designed to reduce the noise level of the output.
  • Optimal input signals are applied to each modulator to provide error masking.
  • The input with high word length is divided into several optimal and smaller parts and each input is applied to a modulator.
  • Since smaller inputs are applied to third- and fourth-order modulators, the hardware consumption is reduced by 17% and power consumption is improved.

Keywords

Main Subjects

References
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Journal of Applied Research in Electrical Engineering
Volume 1, Issue 2
Summer and Autumn 2022
July 2022
Pages 211-220
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History
  • Receive Date: 13 December 2021
  • Revise Date: 03 March 2022
  • Accept Date: 04 March 2022
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